The present invention relates to a solid-state imaging apparatus using an amplification-type MOS sensor for amplifying signal charges within cells.
Recently, compact video cameras and high-resolution, high-vision solid-state imaging apparatuses have been developed. Strong demands have arisen for not only compact cameras and solid-state imaging apparatuses but also low-power-consumption, low-voltage solid-state imaging apparatuses as portable cameras and personal computer cameras.
As the chip size of a solid-state imaging apparatus decreases, however, the amount of signal charge to be processed decreases due to micropatterning. As a result, the dynamic range of the solid-state imaging apparatus narrows, and hence a clear, high-resolution video cannot be obtained. In addition, since many power supply voltages having two, three, or more values are used, a simple system cannot be coped with in terms of camera system configuration and handling. That is, for application to portable cameras and personal computer cameras, a solid-state imaging apparatus which attains a high S/N ratio and uses a single power supply, and also attains reductions in power consumption and voltage is required.
To solve this problem, several amplification-type solid-state imaging apparatuses using transistors have been proposed. These solid-state imaging apparatuses are designed to cause transistors to amplify signals detected by photodiodes in the respective cells, and are characterized by having a high sensitivity.
FIG. 1 is a circuit diagram showing the arrangement of a conventional solid-state imaging apparatus using an amplification-type MOS sensor. Unit cells P0-i-j corresponding to pixels are arranged in the form of a two-dimensional matrix. Although FIG. 1 shows only a 3×3 matrix, the actual apparatus has several thousand cells×several thousand cells. Reference symbol i denotes a variable in the horizontal (row) direction; and j, a variable in the vertical (column) direction. Each unit cell P0-i-j is constituted by a photodiode 1-i-j for detecting incident light, an amplification transistor 2-i-j having a gate to which the cathode of the photodiode 1-i-j is connected and designed to amplify the detection signal, a vertical selection transistor 3-i-j connected to the drain of the amplification transistor 2-i-j to select a horizontal line for reading out the signal, and a reset transistor 4-i-j connected to the cathode of the photodiode 1-i-j to reset the signal charge. The source of the vertical selection transistor 3-i-j and the source of the reset transistor 4-i-j are commonly connected to a drain voltage terminal.
Vertical address lines 6-1, 6-2, . . . horizontally extending from a vertical address circuit 5 are connected to the gates of vertical selection transistors 3-1-1, . . . of the unit cells in the respective rows to determine horizontal lines for reading out signals. Similarly, reset lines 7-1, 7-2, . . . horizontally extending from the vertical address circuit 5 are connected to the gates of reset transistors 4-1-1, . . . in the respective rows.
The sources of amplification transistors 2-1-1, . . . of the unit cells in the respective rows are connected to vertical signal lines 8-1, 8-2, . . . arranged in the column direction. Each of load transistors 9-1, 9-2, . . . is connected to one end of a corresponding one of the vertical signal lines 8-1, 8-2, . . . . A signal output terminal (horizontal signal line) 15 is connected to the other end of each of the vertical signal lines 8-1, 8-2, . . . through horizontal selection transistors 12-1, 12-2, . . . which are driven by horizontal address pulses output from a horizontal address circuit 13.
FIG. 2 is a timing chart showing the operation of this device. When a high-level address pulse is applied to the vertical address line 6-1, only the vertical selection transistors 3 in this line are turned on. As a result, a source follower circuit is constituted by the amplification transistor 2 and the load transistor 9 in this line.
With this operation, the gate voltage of the amplification transistor 2, i.e., almost the same voltage as that of the photodiode 1, appears on the vertical signal line 8.
Horizontal address pulses are sequentially applied from the horizontal address circuit 13 to the horizontal selection transistors 12-1, 12-2, . . . to sequentially output signals corresponding to lines (rows) from the signal output terminal 15. When the signal corresponding to one line is completely read out, a high-level reset pulse is applied to the reset line 7-1 to turn on the reset transistor 4 in this line so as to reset the signal charge.
By sequentially performing this operation for the subsequent lines, all the signals in the two-dimensional matrix can be read out. In this case, a voltage corresponding to almost the same change in the potential of the photodiode 1 appears on the vertical signal line 8. If the capacitances of the photodiode 1 and the vertical signal line 8 are respectively represented by Cs and Cv, the signal charge is amplified Cv/Cs times. In general, Cv is much larger than Cs.
In a solid-state imaging apparatus using an amplification-type MOS sensor of this type, the following problem is posed. As shown in FIG. 1, each unit cell requires at least three transistors, i.e., the amplification transistor 2, the vertical selection transistor 3, and the reset transistor 4. As described above, since the number of transistors constituting each cell is large, this arrangement is not suited for the miniaturization of cells. Although each cell of an MOS-type sensor other than the amplification type is constituted only by a photodiode and a transistor, the sensitivity of the MOS type sensor other than the amplification type is lower than that of the amplification type.
It is an object of the present invention to provide an MOS-type solid-state imaging apparatus which allows a reduction in size.